Method and apparatus for standards conversion of television signals

ABSTRACT

A method of and apparatus for simultaneously enabling different parts of an input television signal to be made available is used as a television standards converter. Successive lines of an input television signal are cyclically written into n (eg 4) successive random access store sections, using in each cycle the same addresses for the different sections. The write addresses are incremented for successive cycles. The sections are read from using for each section addresses which are related to each other and to the write addresses so as to access a desired set of up to n successive lines. These lines are combined by weighted addition to provide an interpolated output line. The read addresses are derived by counting the desired output lines during each field and multiplying the count by the line conversion ratio. The integral part of the resultant controls the read addresses and the non-integral part controls the weighted addition. A total storage of two fields is used, each divided into sections. Standards conversion to either higher or lower lines rates is possible with improved quality.

This invention relates to a method of and apparatus for processingtelevision signals. The invention is particularly, though notexclusively, applicable to standards conversion for converting betweendifferent line, or line and field, standards.

To convert between television signals on different standards, eachpicture point on the output is formed by using the nearest availableinformation from the input signal. To identify the output point in spaceand time, contributions from several lines and several fields areideally required, the number and relative proportions of thesecontributions being selected to optimise the subjective appearance ofthe output picture. This technique is known as interpolation.

This is one example of a situation where it is necessary to providesimultaneously more than one point in a stored television field ornumber of fields.

Existing converters use some form of field storage capable of storing 2to 3 fields, and some additional line storage to give access to severallines at the same time. Thus the two interpolation operations areseparated, namely line interpolation for position, and fieldinterpolation for time.

We have found that the final picture quality resulting from such asystem is bound to be inferior to one in which the completeinterpolation is carried out in one operation. This is because combinedinterpolation permits independent determination of the response atmultiple points in the two-dimensional temporal/vertical response plane.The concept of this two-dimensional sampling theory is introduced in apaper by J. O. DREWERY in B.B.C. Engineering No. 104, September 1976,see particularly pages 15 to 24.

Furthermore, the relative position between lines on the input and outputstandards is continually changing, and the pattern of input line numbersrequired for line interpolation to produce each output line is notregular. When converting from an input standard with a lower number oflines than the output standard, there will be times where it isnecessary to take different proportions of the same group of input linesto form two successive output lines. In the existing converters this isgenerally achieved by providing each of the separate line storageelements with means for recirculating the stored information, andtemporarily stop read out from the field store. When converting in theopposite direction, from a higher to a lower number of lines, pointswill arise where it is necessary to introduce two new input linessimultaneously. This facility is not generally available on existingconverters, some of which avoid the difficulty when operating in thisdirection of conversion by carrying out the line interpolation beforethe field store, and delaying writing into the field store until therequired information becomes available. This requires a major reroutingof signal paths within the converter as between the two directions ofconversion.

With a view to enabling these problems to be more readily overcome, thisinvention is concerned to provide an improved or alternative system forenabling different parts of the field of a television signal to be madeavailable simultaneously.

Accordingly this invention provides a method of an apparatus forsimultaneously enabling different parts of an input television signal tobe made available, in which successive portions (e.g. lines) of theinput television signal are cyclically written into a plurality of (n)successive random access store sections, using in each cycle addressesfor the different sections which are unambiguously related, theaddresses being incremented for successive cycles, and the sections areread from using for each section addresses which are related to eachother and to the write addresses so as to access a desired set of storedsignal portions (eg. lines).

Conveniently the write addresses for all the store sections are the samefor one cycle. If the read addresses are appropriately chosen, nsuccessive lines can be made available simultaneously.

A preferred embodiment of the invention is in the form of a standardconverter in which the outputs read from the store sections are combinedin a weighted addition to provide an interpolated output signal. Thesaid portions are each a television lines and a total storage equal totwo fields is provided, each field of which is divided into cyclicallyaddressed sections as described above. The write addresses are derivedby counting the input lines. The read addresses are particularlyconveniently derived as follows. The desired output lines are countedduring each output field ina counter, and the line count is multipliedby the line conversion ratio, that is the ratio of the number of linesin each input field divided by the number of lines in each output field.The integral part of the resultant will indicate which is the nextadjacent input line to the desired output line, and the non-integralpart will indicate how close that input line is. Thus the former can beused to control the read addresses, and the latter used to control theweighting of the lines read from the store.

The invention will now be described in more detail, by way of example,with reference to the drawings, in which:

FIG. 1 illustrates the contributions from the input lines of two fieldsto locate an output point correctly in time and space;

FIG. 2 shows groups of input lines required to make each output line inthe two directions of conversion; and

FIG. 3 is a block circuit diagram of a television standards converterembodying the invention.

The following description will be made with reference to aninterpolation system in which interpolation is made using four linesfrom each of two input fields. It will be appreciated, however, thatthis is simply one example and that in general interpolation can be madeusing n lines from m fields, where n and m are integers and n≧2,m≧1.

FIG. 1 shows the situation where two input fields and four lines on eachfield are used to generate an output line which is required to bespatially located between the two input fields. In this case it isassumed that there are more output lines per field than input lines, butthis is immaterial.

FIG. 2 illustrates conversion between two standards A and B, where A hasmore lines than B in each field. The figure shows for each input fieldthose lines which are needed, assuming a four line wide interpolationaperture, to form a line of the output field. On the left of the figureare given the lines of a field at the standard B required to formindividual lines of the standard A. Thus this illustrates conversion inthe direction of increasing the number of lines. At the point marked Xthere are two output lines, numbers 7 and 8, which fall in the intervalbetween two input lines, numbers 6 and 7. Thus output lines 7 and 8 mustbe generated from the same set of four input lines, but with differentproportions of the input lines being taken.

On the right of FIG. 2 are given the lines of a field at the standard Arequired to form individual lines of the standard B. Thus thisillustrates conversion in the direction of decreasing the number oflines. At the point marked Y , which is likewise at lines 6 and 7 of thestandard B, there is a point where it is necessary to introduce two newlines of the input standard A, namely lines 7 and 8. That is to say thatthe set of lines 6, 7, 8 and 9 is not used but is omitted from thesteady sequence, which jumps from 5, 6, 7 and 8 to 7, 8, 9 and 10.

Reference will now be made to FIG. 3 which is a block circuit diagram ofa digital television standards converter which embodies the invention.The converter has a video input 10 for receiving a digital televisionsignal at an input standard and which is connected to a buffer store 12.The buffer store 12 which may take the form of a FIFO asynchronous shiftregister (eg Monolithic Memories type 67401), absorbs the frequencydifference between the digital clocking or sample rates of the input andoutput video waveforms, and also makes any small changes which arerequired to the duration of the active period of the television lines.From the buffer store 12 the signal passes to a field phase switch 14,which cyclically applies the fields of the signal to m outputs, in thiscase two, labelled A and B. The A output of switch 14 is applied to aline phase switch 16A which has n outputs, in this case four, numbered1, 2, 3 and 4. The switch 16A cyclically applies the lines of the signalreceived by it to its four outputs. A field store A referenced 20A inthe form of a random access store is connected to the four outputs ofswitch 16A. The field store is divided into n (=4) sections labelledBlocks 1, 2, 3 and 4. Associated with the inputs to he blocks is writeaddressing circuitry 18A which controls the location at whichinformation is stored within each block. Associated with the outputs ofthe blocks is read addressing circuitry 22A which controls the locationfrom which information is read from each block. Each block has its ownoutput 24A1 to 24A4 respectively, and to each output is connected amultiplier 26A1 to 26A4 respectively. The other input of each multiplieris connected to a respective output of a multiplier coefficientgenerator 30 which takes the form of a programmable read only memory(PROM). The outputs of the multipliers 26A are summed by three adders28A connected as shown. The resultant output 32A is then applied to oneinput of a final adder 34. It will be appreciated that other circuitconfigurations can be used to add the store outputs with the requiredweights specified by the coefficient generator 30.

To the output B of the field phase switch 14 is connected an identicalseries of circuit elements, which are accordingly referenced with theletter B. These comprise a line phase switch 16B, random access fieldstore 20B having four blocks with write addressing circuitry 18B andread addressing circuitry 22B, output lines 24B1 to 24B4, multipliers26B1 to 26B4 connected to respective lines 24B1 to 24B4 on the one handand to respective outputs B1 to B4 of the multiplier coefficientgenerator 30 on the other, and adders 28B providing an output on line32B which is applied to the other input of adder 34. The output 36 ofthe adder 34 constitutes the video output of the converter.

The converter as thus-far described operates as follows. It is seen thateach field store 20 is divided into four sections, so that there can befour simultaneous read outputs. During the writing process, for eachfield received by switch 16A (for example), successive lines of theinput signal are cyclically written in turn into the successive blocksof the store 20A. Thus line 1 is written into block 1, line 2 into block2, line 3 into block 3, line 4 into block 4, line 5 again into block 1,line 6 into block 2, and so on. In the general case, therefore, line4i+1 is written into block 1, line 4i+2 into block 2, line 4i+3 intoblock 3, and line 4i+4 into block 4 (i being an integer). Each block hasa capacity of at least one quarter of the number of lines in an inputfield, rounded up to the next integer, and each line is separatelyaddressable. For each cycle of switch 16A, that is for each value of i,the same store address can be used to denote corresponding locations ineach block. Thus the write address received by the circuitry 18A remainsconstant during each cycle and increments by one at the end of eachcycle, after block 4.

To gain access to a group of four successive input lines forinterpolation, each block or section of the store has an independentoutput 24A. The read address circuitry 22A simultaneously addresses oneinput line of each of the four blocks to provide four lines. Normallyfor output line 4i', each block is addressed with the same address i'.For line 4i'+1, block 1 is addressed with the address i'+11, and theremaining blocks 2 to 4 are addressed with address i'. For the nextsubsequent line 4i'+2, blocks 1 and 2 are addressed with the addressi'+1, and blocks 3 and 4 are addressed with the address i'. Thiscontinues cyclically, such that the address change "ripples through" thesections of the store as each successive group of stored input lines isread to form an output line.

It will be seen therefore that the problems arising at points X and Y onFIG. 2 can readily be overcome by altering the steady sequence of theread addresses. To repeat a line as required at X , all that isnecessary is to fail to alter the read addresses between one output lineand the next. To make a jump as required at Y , the read address for thenext two blocks are both incremented simultaneously.

The operation as applied above can be applied in parallel to twosuccessive input fields simultaneously. The same write and readaddresses can be used in the two field stores 20A and 20B, although themultiplier coefficients will differ. The totals of the weightedcontributions from the two fields are summed in the adder 34.

It should be noted that while the field and line phase switches 14, 16Aand 16B have been illustrated as mechanical switches, normally they willbe implemented electronically. For example the input to switch 14 may beapplied to all eight store sections, but the control signals shown asapplied to the switches are used to enable writing into only the sectionwhich is appropriate at that particular time. Also, the outputs of theblocks are preferably subjected to a small but successively increasingdelay, as to compensate for the delays in the chain of adders 28. Thebuffer circuit 12 is only required when, as here, the field stores 20Aand 20B write and read on the same clock frequency. The buffer store isnot required if the stores have asynchronous capability.

A number of advantages result from the construction of the converterdescribed. These include the following:

(1) Combined line and field interpolation is achieved.

(2) No separate line delays are required. This results in a cheaper andsimpler store.

(3) There is no necessity to separate the line (positional) and field(temporal) interpolation functions or interchange their order whenreversing the direction of conversion.

(4) Simple control logic will allow complete freedom to repeat groups oflines or jump forward in the sequence.

(5) The ability exists to provide timing offsets (delays) between storesection outputs to simplify `ripple adding` after the interpolationmultipliers 26.

(6) There is no complicated signal path switching when changingdirection of conversion.

(7) Storage of complete fields of the input standard allows greaterflexibility in dealing with input signal irregularities.

The control circuitry for the converter will now be described withfurther reference to FIG. 3. Also connected to the input terminal 10 isa synchronising (sync.) pulse separator 50 which provides, over tworespective outputs, pulses at the field frequency and pulses at the linefrequency, these pulses in each case occurring between lines at thestart of each field and line respectively. The line frequency pulses areapplied to a line counter 52 which has a first or most significant bits(MSB) output which indicates the next lowest multiple of 4 to thecurrent line number (i.e. the value i above), and a second or leastsignificant bits (LSB) output which indicates the difference between thecurrent line number and the said multiple of 4. The LSB output indicatesthe block to which the current line is to be applied, and is accordinglyused to control the switches 16A and 16B. The MSB output indicates thecurrent write address and is accordingly applied to the write addressingcircuitry 18A and 18B of the stores 20A and 20B.

The field frequency pulses from sync. separator 50 are applied to afield counter 54 (in principle simply a bistable flip-flop circuit) theoutput of which controls the field phase switch 14. The field frequencypulses are also used to reset to zero the line counter 52.

An input 56 receives in any convenient form an output reference signal.If this is in full video form, then a sync. separator 58, similar to theseparator 50, is used to provide line and field frequency pulses withthe required output timing. A second line counter circuit 60 counts theline pulses and is reset to zero by each field pulse. The line count isapplied to a control multiplier 62 which receives from an input 64 asignal representing the ratio of the number of lines in a field of theinput line standard divided by the number of lines in a field of theoutput line standard. (This could be derived from the signals at inputs10 and 56). The result of this multiplication specifies the relation ofthe current output line to the input lines. The integral part of theresultant, the MSB output of multiplier 62, specifies the nearest storedinput line above the output line required and is accordingly applied tothe read addressing circuitry 22A and 22B of the stores 20A and 20B. Thefractional part, or residue, represents the distance between the outputline and the adjacent input lines and is accordingly applied to themultiplier coefficient generator 30. As the conversion proceeds, therepeats and jumps denoted by X and Y in FIG. 2 in the series ofaddresses for the stored lines appear as a natural consequence of themultiplication process.

Finally, a temporal aperture processor 66 receives the input fieldfrequency pulses from counter 54, the MSB output of input line counter52, and the MSB output of the multiplier 62, and determines the timeinstant which is midway between the earliest and latest informationavailable to be read from the store. The output of processor 66 definesthe remainder of the address for the set of interpolation coefficientsand is thus also applied to the coefficient generator 30. The temporaladdress is obtained by comparing the input line number with the quotientof the multiplication on the MSB output of multiplier 62. Thiscomparison will show whether the lines read from the field being writtenare `old` or `new`. The coefficient set is also defined by the currentinput line number since the centre of the aperture is at a time one halfthe total storage before the current writing point. The coefficient areread out from the generator 30 line-by-line into buffer registersassociated with the individual multipliers 26.

In principle the method described above can be applied to converterswhich use only one field store, the other field store being omitted. Theinvention then enables the simultaneous availability of and henceinterpolation between successive lines of a single field. Conversely themethod can be extended to include more than two fields, to enableinterpolation between successive pictures of an interlaced-fieldstandard for example.

What we claim is:
 1. A method of simultaneously enabling different partsof an input video signal to be made available, using signal storage,comprising the steps of:cyclically writing successive .[.portions.]..Iadd.lines .Iaddend.of the input video signal relating to successiveportions of the video picture into .Iadd.successive ones of .Iaddend.aplurality of .[.successive.]. random access store sections, each ofwhich is capable of storing several video lines but less than one field,.Iadd.said sections providing a total storage of at least twoconsecutive fields, .Iaddend.using in each cycle .[.write addressesfor.]. .Iadd.essentially the same write address sequences within.Iaddend.the different sections .[.which are unambiguously related.].;incrementing the write addresses for successive cycles; and reading fromthe .Iadd.store .Iaddend.sections using for each section read addresseswhich are related to each other and to the write addresses so as.Iadd.simultaneously .Iaddend.to access a desired set of .[.storedsignal portions.]. .Iadd.line samples from corresponding positions froma plurality of stored lines with each line sample of the set being readfrom a different store section.Iaddend.. .[.2. A method according toclaim 1, wherein each signal portion is a video signal line..]. .[.3. Amethod according to claim 1, wherein the write addresses for all thestore sections are the same for one cycle..].
 4. A method according toclaim .[.3.]. .Iadd.1.Iaddend., wherein the read addresses are so chosenthat several successive lines, equal in number to the number of storesections, are made available simultaneously.
 5. A method according toclaim 1, wherein a total storage of two fields or pictures is provided,each field of which is divided into store sections.
 6. A methodaccording to claim 1, wherein several outputs read from the storesections are combined in a weighted addition to provide an interpolatedoutput signal.
 7. A method according to claim 6, wherein the weightingis controlled by counting the desired output lines during each outputfield, multiplying the count by the line conversion ratio, andcontrolling the weighting in dependence upon the non-integral part ofthe resultant.
 8. A method according to .[.claim.]. .Iadd.claims.Iaddend.1, .Iadd.4, 5, 6 or 7 .Iaddend.wherein the read addresses arederived by counting the desired output lines during each output field,multiplying the count by the line conversion ratio, and selecting theread address in dependence upon the integral part of the resultant. 9.Apparatus for simultaneously enabling different parts of an input videosignal to be made available and comprisingsignal storage means, thesignal storage means comprisinga plurality of random access storesections; writing means for cyclically writing successive .[.portions.]..Iadd.lines .Iaddend.of the input video signal relating to successiveportions of the video picture into successive .Iadd.ones of said.Iaddend.random access store sections, each of which is capable ofstoring several video lines but less than one field, .Iadd.said sectionsproviding a total storage of at least two consecutive fields,.Iaddend.using in each cycle .[.write addresses for.]. .Iadd.essentiallythe same write address sequences within .Iaddend.the different.Iadd.store .Iaddend.sections .[.which are unambiguously related.].;means for incrementing the write addresses for successive cycles; andreading means for reading from the sections using for each section readaddresses which are related to each other and to the write addresses soas .Iadd.simultaneously .Iaddend.to access .Iadd.from each stored field.Iaddend.a desired set of .[.stored signal portions.]. .Iadd.linesamples from corresponding positions from a plurality of stored lineswith each line sample of the set being read from a different storesection.Iaddend..
 0. Apparatus according to claim 9, wherein there is atotal storage of two fields or pictures, each field of which is dividedinto store sections. Apparatus according to claim 9, including means forcombining several outputs from the store sections in a weighted additionto provide an interpolated output signal.
 12. Apparatus according toclaim 11, including a counter for counting the desired output linesduring each output field, a multiplier for multiplying the count by theline conversion ratio, and means for controlling the weighting performedby the combining means in dependence upon the non-integral part of themultiplier output.
 13. Apparatus according to claim 9, including acounter for counting the desired output lines during each output field,and a multiplier for multiplying the count by the line conversion ratio,and wherein the reading means selects the read address in dependenceupon the integral part of the multiplier output.
 14. A method ofsimultaneously enabling different parts of an input video signal to bemade available, using signal storage, comprising the steps ofcyclicallywriting successive .[.portions.]. .Iadd.lines .Iaddend.of the inputvideo signal relating to successive portions of the video picture into.Iadd.successive ones of .Iaddend.a plurality of .[.successive.]. randomaccess store sections, .Iadd.said sections providing a total storage ofat least two consecutive fields, .Iaddend.using in each cycle .[.writeaddresses for.]. .Iadd.essentially the same write address sequenceswithin .Iaddend.the different .Iadd.store .Iaddend.sections which areunambiguously related, the write addresses for all the store sectionsbeing the same for one cycle, incrementing the write addresses forsuccessive cycles; and reading from the .Iadd.store .Iaddend.sectionsusing for each section read addresses which are related to each otherand to the write addresses so as .Iadd.simultaneously .Iaddend.to access.Iadd.from each stored field .Iaddend.a desired set of .[.stored signalportions.]. .Iadd.line samples from corresponding positions from aplurality of stored lines with each line sample of the set being readfrom a different store section.Iaddend..
 5. A method of simultaneouslyenabling different parts of an input video signal to be made available,using signal storage, comprising the steps ofcyclically writingsuccessive portions of the input video signal relating to successiveportions of the video picture into a plurality of successive randomaccess store sections, using in each cycle write addresses for thedifferent sections which are unambiguously related; incrementing thewrite addresses for successive cycles; and reading from the sectionsusing for each section read addresses which are related to each otherand to the write addresses so as to access a desired set of storedsignal portions, the read addresses being derived by counting thedesired output lines during each output field, multiplying the count bythe line conversion ratio, and selecting the read address in dependenceupon the integral part of the resultant.
 16. Apparatus forsimultaneously enabling different parts of an input video signal to bemade available and comprisingsignal storage means, the signal storagemeans comprisinga plurality of random access store sections; writingmeans for cyclically writing successive portions of the input videosignal relating to successive portions of the video picture intosuccessive random access store sections, using in each cycle writeaddresses for the different sections which are unambiguously related;means for incrementing the write addresses for successive cycles;reading means for reading from the sections using for each section readaddresses which are related to each other and to the write addresses soas to access a desired set of stored signal portions; and furtherincluding a counter for counting the desired output during each outputfield, and a multiplier for multiplying the count by the line conversionratio, and wherein the reading means selects the read address independence upon the integral part of the multiplier output. .[.17. Amethod of simultaneously enabling different parts of an input videosignal to be made available, using signal storage having a storagecapacity of substantially one video field, comprising the steps ofcyclically writing successive portions of the input video signalrelating to successive portions of the video picture into a plurality ofsuccessive random access store sections, using in each cycle writeaddresses for the different sections which are unambiguously related;incrementing the write addresses for successive cycles; and reading fromthe sections using for each section read addresses which are related toeach other and to the write addresses so as to provide simultaneousaccess to one stored signal portion only in each store section..]..[.18. A method according to claim 17 wherein each signal portion is avideo signal line..]. .[.19. A method according to claim 17 wherein theread addresses are so chosen that several successive lines, equal innumber to the number of store sections, are made availablesimultaneously..]. .[.20. A method according to claim 17 wherein severaloutputs read from the store sectons are combined in a weighted additionto provide an interpolated output signal..]. .[.21. A method accordingto claim 17 wherein the weighting is controlled by counting the desiredoutput lines during each output field, multiplying the count by the lineconversion ratio, and controlling the weighting in dependence upon thenon-integral part of the resultant..]. .[.22. Apparatus forsimultaneously enabling different parts of an input video signal to bemade available and comprisingsignal storage means, the signal storagemeans having a storage capacity of substantially one video field andcomprisinga plurality of random access store sections; writing means forcyclically writing successive portions of the input video signalrelating to successive portions of the video picture into successiverandom access store sections, using in each cycle write addresses forthe different sections which are unambiguously related; means forincrementing the write addresses for successive cycles; and readingmeans for reading from the sections using for each section readaddresses which are related to each other and to the write addresses soas to provide simultaneous access to one stored signal portion only ineach store section..]. .[.23. Apparatus according to claim 22, includingmeans for combining several outputs from the store sections in aweighted addition to provide an interpolated output signal..]. .[.24.Apparatus according to claim 22, including a counter for counting thedesired output lines during each output field, a multiplier formultiplying the count by the line conversion ratio, and means forcontrolling the weighting performed by the combining means in dependenceupon the non-integral part of the multiplier output..].